Date

Thursday 20th October @ 14:00 – 15:00 (UK time)

Presenter

Prof. Syed Waqar Nabi

Affiliation

University of Glasgow

Location

Online link: https://welink.zhumu.com/j/189695019

Note: this is a talk open to the public.

Abstract

I will talk primarily about the work I did during my postdoc in the EPSRC funded “TyTra” project, which had the aim of developing an optimizing compiler for running legacy scientific code (mostly Fortran) on heterogenous devices. For a complete narrative, I will first briefly discuss the front-end part of this work — other very smart people worked on it — which looked at extracting functional patterns from legacy Fortran code. I will then focus on my own work on the middle and back ends. We developed a custom intermediate language called “TyTra-IR” that took inspiration from LLVM-IR, with customizations added specific to FPGA device target. I will present some details of the cost-model developed to evaluate design-variants expressed in this IR, and then describe the backend code generator that generated code in multiple languages and abstractions. I will show the back-end in action, and discuss briefly how it was developed using Perl (and would love to hear thoughts on how this approach could be generalized for other domains). I will also discuss some related off-shoots of this project that I worked on, and possibly one or two quite unrelated side projects just for interest. Finally, I will use this opportunity to share some personal reflections on research: vision, approach, impact.

Short Bio

Waqar is a Lecturer at and alumnus of the School of Computing Science, University of Glasgow. He is a member of Glasgow Parallelism research group (GPG) of Systems Research Centre (GLASS), and also the Centre for Computing Science Education (CCSE). He teaches for the BSc (Hons) Software Engineering (Graduate Apprenticeship) program. Earlier, he was a postdoc at the same School on the EPSRC funded project “Exploiting Parallelism through Type Transformations for Hybrid Manycore Systems”. For his doctorate dissertation, he developed a System-on-Chip’s high-level architecture for MAC layer processing in handheld devices.

【ERC Coffee House】Intermediate Language, Cost Model, and Code Generator for Heterogenous Computing / Huawei-Edinburgh Joint Lab by blogadmin is licensed under a Creative Commons Attribution CC BY 3.0